# -*- mode:python -*-

# Copyright (c) 2013 ARM Limited
# Copyright (c) 2014 Sven Karlsson
# Copyright (c) 2020 Barkhausen Institut
# Copyright (c) 2021 Huawei International
# Copyright (c) 2024 University of Rostock
# All rights reserved
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder.  You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2016 The University of Virginia
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Import('*')

if not env['CONF']['USE_RISCV_ISA']:
    Return()

env.TagImplies('riscv isa', 'gem5 lib')

env.TagImplies('isa', 'riscv isa')

Source('decoder.cc', tags=['riscv isa'])
Source('faults.cc', tags=['riscv isa'])
Source('interrupts.cc', tags=['riscv isa'])
Source('isa.cc', tags=['riscv isa'])
Source('process.cc', tags=['riscv isa'])
Source('pagetable.cc', tags=['riscv isa'])
Source('pagetable_walker.cc', tags=['riscv isa'])
Source('pma_checker.cc', tags=['riscv isa'])
Source('pmp.cc', tags=['riscv isa'])
Source('reg_abi.cc', tags=['riscv isa'])
Source('remote_gdb.cc', tags=['riscv isa'])
Source('semihosting.cc', tags=['riscv isa'])
Source('tlb.cc', tags=['riscv isa'])

Source('linux/se_workload.cc', tags=['riscv isa'])
Source('linux/fs_workload.cc', tags=['riscv isa'])

Source('bare_metal/fs_workload.cc', tags=['riscv isa'])

SimObject(
    'PMAChecker.py',
    sim_objects=['PMAChecker', 'BasePMAChecker'],
    tags=['riscv isa']
)
SimObject('PMP.py', sim_objects=['PMP'], tags=['riscv isa'])
SimObject(
    'RiscvDecoder.py',
    sim_objects=['RiscvDecoder'],
    tags=['riscv isa']
)
SimObject(
    'RiscvFsWorkload.py',
    sim_objects=['RiscvBareMetal', 'RiscvLinux',
                 'RiscvBootloaderKernelWorkload'],
    tags=['riscv isa']
)
SimObject(
    'RiscvInterrupts.py',
    sim_objects=['RiscvInterrupts'],
    tags=['riscv isa']
)
SimObject(
    'RiscvISA.py',
    sim_objects=['RiscvISA'],
    enums=['RiscvType', 'PrivilegeModeSet'],
    tags=['riscv isa']
)
SimObject(
    'RiscvMMU.py',
    sim_objects=['RiscvMMU'],
    tags=['riscv isa']
)
SimObject(
    'RiscvSemihosting.py',
    sim_objects=['RiscvSemihosting'],
    tags=['riscv isa']
)
SimObject(
    'RiscvSeWorkload.py',
    sim_objects=['RiscvSEWorkload', 'RiscvEmuLinux'],
    tags=['riscv isa']
)
SimObject(
    'RiscvTLB.py',
    sim_objects=['RiscvPagetableWalker', 'RiscvTLB'],
    tags=['riscv isa']
)

SimObject('RiscvCPU.py', sim_objects=[], tags=['riscv isa'])

DebugFlag('RiscvMisc', tags=['riscv isa'])
DebugFlag('PMP', tags=['riscv isa'])

# Add in files generated by the ISA description.
ISADesc('isa/main.isa', tags=['riscv isa'])
